Switched-capacitor networks are generally applied in signal filtering. Signal filters with the switched-capacitor networks are also named charge domain filters.
FIG. 1A depicts an example of a switched-capacitor network and FIG. 1B shows control signal waveforms for the circuit of FIG. 1A. As shown, N control signals clk1 . . . clkN are used in the control of the switched-capacitor network 100. FIG. 1B shows that the N clock signals clk1 . . . clkN are periodic signals and are active at different times. Thus, N control phases are provided. The control signals clk1 . . . clk(N−2) provide signal input phases. According to the control signals clk1 . . . clk(N−2), an input signal IN electrifies the capacitors C1 . . . C(N−2) in turn. The control signal clk(N−1) provides a charge summation phase. According to the control signal clk(N−1), the electric charges stored in the capacitors C1 . . . C(N−2) is further transmitted to the capacitor Cout at the output terminal (OUT) of the switched-capacitor network 100. The control signal clkN provides a reset phase. According to the control signal clkN, the capacitors C1 . . . C(N−2) are discharged for the succeeding signal input phases. Referring to the first waveform shown in FIG. 1B, a system clock clk is shown. The input clock rate (represented by ICR) determines the length of a clock period (1/ICR). Because a time period N/ICR is required to refresh the output signal OUT, a sample rate decimation exists in the switched-capacitor network 100.
To solve the sample rate decimation, several techniques have been developed. One well-known technique is the “interleaving technique.” FIG. 2 shows a charge domain filter 200 using the interleaving technique. There are six circuits 202_1 . . . 202_6, which are identical and share an output capacitor Cout, and each requires six phases (clk1 . . . clk6). It has to be noted that the circuits 202_1 . . . 202_6 are controlled in an interleaving form, to make the circuits 202_1 . . . 202_6 connect to the output capacitor Cout at different times. When looking at the turning-on order of the switches of the circuit 202_1 and the turning-on order of the switches of the circuit 202_2, there is one phase shift. Similarly, when looking at the turning-on order of the switches between the circuits 202_2 and 202_3, between the circuits 202_3 and 202_4, between the circuits 202_4 and 202_5, between the circuits 202_5 and 202_6, and between the circuits 202_6 and 202_1, there is one phase shift. The circuits 202_1, 202_2, 202_3, 202_4, 202_5 and 202_6 are connected to the output capacitor Cout according to the control signals clk5, clk6, clk1, clk2, clk3, and clk4, respectively. The output signal OUT is refreshed at every control phase, so that no sample rate decimation occurs in the charge domain filter.
In addition to the basic switched-capacitor network 100 or the interleaving technique of FIG. 2, there are many variants and types of charge domain filters. For charge domain filter designs, there are two important issues: leakage reduction and controllable transfer functions. This specification could provide charge domain filters with good leakage reduction performance and providing controllable transfer functions.